The present invention relates to electronic circuits, and more particularly to detection of a control voltage in a closed loop circuit, such as a phase locked or delay locked loop.
The increasing speed with which multiple types of data, such as text, audio and video, are transported over existing communication networks has brought to the fore the reliability with which such data transportation is carried out. In accordance with one conventional method, to ensure reliable data transfer, the data is first encoded with a reference clock signal at the transmitting end of the network to generate a composite signal. Thereafter, the composite signal is transmitted over the network to the receiving end. At the receiving end, the data and clock signals are recovered from the composite signal to ensure that the data and clock signals remain synchronous with respect to each other.
The clock and data recovery is typically carried out, for example, by a delay locked loop or a phase locked loop. In operation, a phase locked loop maintains a fixed relationship between the phase and frequency of the signal it receives and those of the signal it generates. FIG. 1 is a simplified block diagram of a conventional phase locked loop (PLL) 10 adapted to maintain a fixed relationship between the phase and frequency of signal CLK and signal Ref_Clk. PLL 10 includes, among other components, phase detector 12, charge pump 14, loop filter 16 and voltage controlled oscillator (VCO) 18. The extracted clock signal Clk is supplied at the output terminal of VCO 18. Once in a locked state, the phase and frequency of signal Clk generated by PLL 10 is locked to those of signal Ref_Clk received by PLL 10. The operation of PLL 10 is described further below.
Phase detector 12 receives signals Ref_Clk and Clk, and in response, generates signal A that corresponds to the difference between the phases of these two signals. Charge pump 14 receives signal A and in response generates and delivers to node B a current signal whose duration varies depending on the magnitude of signal A. Loop filter 16 filters out the high frequency components of signal I and delivers a filtered-out voltage signal to VCO 18.
If signal Ref_Clk leads signal Clk in phase—indicating that the VCO is running relatively slowly—signal A causes charge pump 14 to increase its output current until VCO 18 achieves an oscillation frequency at which signal Clk is frequency-locked and phase-locked with signal Ref_Clk. If, on the other hand, signal Ref_Clk lags signal Clk in phase—indicating that the VCO is running relatively fast—signal A causes charge pump 14 to reduce its output current until VCO 18 achieves an oscillation frequency at which signal Clk is frequency-locked and phase-locked with signal Ref_Clk. Signal Clk is considered to be locked to signal Vref if its frequency is within a predetermined frequency range of signal Ref_Clk. Signal Clk is considered to be out-of-lock with signal Ref_Clk if its frequency is outside the predetermined frequency range of signal Ref_Clk.
FIG. 2 is a simplified block diagram of another conventional PLL 30 that includes, among other components, phase/frequency detector 32, charge pump 34, loop filter 36, voltage to current (VTI) converter 38, current controlled oscillator (ICO) 40, and out-of-range voltage detection circuitry 42. In PLL 30, voltage Vcont is generated by charge pump 34. Out-of-range voltage detection circuitry 42 is adapted to detect whether voltage Vcont is within a range defined by voltage Vbg. Determination of voltage Vcont provides insight into the loop dynamics, enables control of the loop voltage, and allows PLL 30 to be calibrated. In response, voltage detection circuitry 42 generates voltage signals Vcom1 and Vcom2. VTI converter 38, using voltage Vref, converts the voltage Vcont to a current I, and delivers this current to ICO 40.
FIG. 3 is a transistor schematic diagram of VTI circuit 38, as known in the prior art. VTI circuit 38 is shown as including a differential amplifier formed by NMOS transistors 120, 122 and resistor 118, current source 200, current mirrors 205, 210, 215, 220, 225, and biasing transistor 106. Assume current source 200, which is a cascade current source generates a current of 2I that flows through PMOS transistors 102, 104. Current mirrors 205, 220, and 225 mirror this current, and therefore, a current of 2I also flows through PMOS transistors 108, 128, and 130. Part of the current 2I mirrored in transistor 128 flows through PMOS transistor 124—shown as current I+DI—the remainder of this current flows through transistor 120—shown as current I−DI. Similarly, part of the current 21 mirrored in transistor 130 flows through PMOS transistor 126—shown as current I−DI—the remainder of this current flows through transistor 122—shown as current I+DI. Because the same current flows through both PMOS transistor 124 and NMOS 132, a current of I+DI flows through transistor 132. Moreover, because the same current flows through NMOS transistors 132, and 134, a current of I+DI flows through transistor 134.
NMOS transistors 114, and 116 are scaled relative to NMOS transistor 112, such that each conduct a current of I. If voltage Vcont is greater than voltage Vref, more current, e.g., I+DI flows through transistor 122 and less current, e.g., I−DI flows through transistor 120. Similarly, if voltage Vcont is smaller than voltage Vref, more current flows through transistor 120 and less current flows through transistor 122. Because the current through transistors 114 and 116 is adapted to be I, a current of DI flows through resistor 118 and transistor 116. It is understood that depending on the relative sizes of voltages Vcont and Vref, shown current DI may have a positive or a negative value. The difference 2DI between current I−DI flowing through transistor 126 and current of I+DI flowing through transistor 134, flows to terminal Icntl if current DI is negative, or from terminal Icntl if DI is positive. Therefore, the difference between voltages Vcont and Vref, results in change in the current 2DI flowing into or out of terminal Icntl.
FIG. 4 shows the change in the current flowing through terminal Icntl as a function of the difference between voltages Vcnt and Vref. The current flow through terminal Icnt varies linearly as a function of the difference between voltages Vcnt and Vref, so long as this voltage difference is between ±Vd. A constant current of 2I flows through this terminal if the magnitude of the difference between voltages Vcnt and Vref exceeds Vd.
FIG. 5 is a schematic diagram of voltage detection circuitry 42, as known in the prior art. Band-gap voltage generator 52 generates reference voltage Vbg that is applied to positive input terminal Inp of operational amplifier (op-amp) 54. The output voltage of op-amp 54 is applied to the gate terminal of PMOS transistor 60. Upper boundary voltage Vcom_hi is applied to the positive input terminal Inp of voltage comparator 66, and lower boundary voltage Vcom_lo is applied to the positive input terminal Inp of voltage comparator 68. Voltage signal Vcont is applied to the negative input terminals Inn of both voltage comparators 66 and 68. If voltage Vcont is greater than voltage Vcom_hi, output signals Vcom1 and Vcom2 make a high-to-low transition. If voltage Vcont is smaller than voltage Vcom_lo, output signals Vcom1 and Vcom2 make a low-to-high transition. If voltage Vcont is between voltages Vcom_lo and Vcom_hi, output signal Vcom1 remains high and output signal Vcom2 remains low.
As seen from FIG. 5, out-of-range detection circuitry 42 requires, among other components, one op-amp, two voltage comparators, as well as a band-gap circuit. Therefore, out-of-range detection circuitry 42 is relatively large, i.e., consumes a relatively large semiconductor surface area, and also consumes a relatively large power.